AMD's Zen 6 architecture marks a significant shift in how the company balances performance and area, moving toward a dual-core family strategy that distinguishes between high-frequency designs and dense technology cores. By leveraging denser technology to provide the highest possible Instructions Per Cycle (IPC) and 4MB of L3 cache per core, the Zen 6 family aims to maximize performance in high-density configurations while maintaining a separate path for high-frequency targets.
The Zen 6 Core Family Strategy
Starting with Zen 4, AMD has evolved toward a two-core family model. In the Zen 6 generation, the dense technology core is positioned as the top-of-the-line performance core, featuring 4MB of L3 cache per core and the highest available IPC.
To ensure software remains compatible across both architectures, AMD maintains a consistent 'fit and feel' for optimizations. However, the Zen 6c variant utilizes larger capacity in the floating-point scheduler and other queues to compensate for its reduced frequency target.
“So we have 32 of those cores, 128MB of L3, and the highest IPC you can get in that core.”
— Talking Zen 6 with Mike Clark at AMD In-Depth
Front End and Execution Engine Refinements
The Zen 6 front end builds on the dual decode foundation of Zen 5 but focuses on power efficiency and delivery. The team optimized the system to better handle large-footprint workloads where instructions may hit the I-cache and op-cache simultaneously.
In the execution engine, AMD reduced the number of integer multiply units from three to two. This change was driven by a move back to distributed schedulers, which required more uniform units to simplify the scheduling logic and optimize the overall floor plan.
AI Capabilities and Vector Performance
AMD added two more VNNI (Vector Neural Network Instructions) units to the Zen 6 core. While the core is not intended to replace GPUs for AI, these units enhance the processor's ability to handle orchestration, data type manipulation, and smaller model inference.
The core also achieved a long-standing goal of supporting four 256-bit vector loads per cycle. This was made possible by utilizing existing wire paths from the Zen 5 design, which had already supported two 512-bit loads.
L3 Cache and Memory Bandwidth
To ensure the L2 cache can consistently deliver 64 bytes per cycle, AMD modified the prefetching logic. This prevents prefetches from 'robbing' bandwidth from demand requests, ensuring sustained performance during heavy cache access.
While AMD confirmed that the design includes tricks to maintain bandwidth within the L3 mesh and mitigate increased latencies in larger CCDs (Core Complex Dies), the specific technical implementations of these mechanisms remain proprietary.