Esp32sim is an open-source emulator designed to run firmware for several Espressif SoCs, including the classic ESP32, the ESP32-S3 (Xtensa LX7 architecture), and the RISC-V based ESP32-C3 and ESP32-C6. Unlike many high-level software simulators that only mimic specific APIs or functional behaviors, Esp32sim provides instruction-level emulation. This allows it to boot the actual mask ROM, the second-stage bootloader, and unmodified application images, providing a high-fidelity environment for end-to-end project testing.
This image represents the Esp32sim project, which provides instruction-level emulation for various Espressif SoCs.
The emulator is built in Rust and utilizes a combination of interpreters and Just-In-Time (JIT) compilation to achieve performance. For the ESP32-S3, it employs an AArch64 JIT to reach speeds of approximately 150–240 Minsn/s. The system models a wide array of peripherals shared across these chips, such as GPIO, UART, timers, and SPI flash controllers. It also includes specialized models for the ESP32-S3's LCD and camera interfaces, enabling developers to run complex projects—such as a pedestrian detector using the PIE SIMD unit—entirely in a virtual environment.
One of the project's most distinct features is its ability to run in a web browser via WebAssembly. This allows for a zero-install experience where users can interact with a virtualized environment including a console, audio, and even a simulated WiFi access point. The networking stack supports WPA2, DHCP, and NAT, allowing the emulated firmware to communicate with the host's real network. While it provides a powerful alternative to physical prototyping, the emulator currently operates at a speed significantly faster than real-time (e.g., ~30x faster for certain boot cycles), and some specific hardware-dependent features, such as the PHY's baseband calibration for the C6, still require hardware-specific stubs or remain unsupported in the virtual environment.
The emulator supports a zero-install experience via WebAssembly, allowing users to interact with a virtualized environment in a browser.
Because it supports the full boot sequence, Esp32sim is particularly useful for CI/CD pipelines where developers need to verify that firmware behaves correctly across different boot stages without deploying to physical boards. It provides a bridge between high-level functional simulators and physical hardware, offering a way to test real binary files in a reproducible, local, or browser-based environment. The project is licensed under MIT, making it accessible for both personal and commercial development workflows.
Key technical specifications and supported boards include: - **ESP32-S3**: Dual-core Xtensa LX7 @ 240 MHz, supporting boards like the Waveshare LCD4B and various camera modules. - **ESP32-C3**: Single-core RISC-V RV32IMC @ 160 MHz. - **ESP32-C6**: Single-core RISC-V RV32IMAC @ 160 MHz, featuring 802.15.4 and WiFi MAC support. - **Networking**: Virtual APs with WPA2, DHCP, and NAT relaying to the host network.
Users can run the emulator via a command-line interface, specifying the chip and board types. For example, running an ESP32-S3 project involves pointing the emulator to the mask ROM, bootloader, and application binaries, which then executes the code and outputs logs to a virtual UART0 console. This setup allows for rapid iteration on firmware logic before moving to final hardware deployment.
While the emulator is mature for the ESP32-S3, the C3 and C6 models are currently in a draft status. These models share many peripheral components with the S3 but include unique memory maps, cache controllers, and interrupt matrices. The emulator's ability to reproduce hardware-specific behaviors, such as RTC watchdog resets and specific console output lines, has been verified against physical modules through JTAG traces and console diffs, ensuring a high degree of accuracy for the primary development workflows.
What remains uncertain or limited includes the exact performance overhead of the WebAssembly implementation compared to the native Rust binary, and the full coverage of the RISC-V instruction set for the C6 model, which is still being refined. Additionally, while the emulator handles most standard peripherals, highly specialized analog components or specific PHY-layer calibrations that require physical radio hardware still necessitate the use of physical boards or specific software stubs.
Ultimately, Esp32sim serves as a tool for