A technical investigation into the Loongson LA664 CPU core—used in the 3C6000/S and 3A6000 series—has revealed a hardware erratum involving the failure of atomic instructions. The issue manifests as a 'lost update,' where an atomic operation (such as an addition) fails to correctly register a change to a shared variable. This was first observed during the packaging of the `normaliz` math software for Debian, where a parallel processing loop became stuck in an infinite loop because a counter variable failed to reach its expected value despite all data points being processed.
This image illustrates the specific hardware erratum identified in the Loongson LA664 CPU core regarding lost atomic updates.
The root cause was identified as a specific interaction between the CPU's atomic instructions and vectorized memory operations. Specifically, the `amadd` (atomic add) instruction can lose updates when executed across different physical cores without a data barrier, provided that at least one thread interleaves a specific type of memory read between its atomic operations. While the LASX 256-bit vectorized memory read (`xvld`) was the primary trigger identified, further testing showed that even standard scalar reads could trigger the issue if the memory addresses of the atomic variable and the read operation share a particular positional relationship. This complexity explains why the bug remained hidden during initial testing.
Loongson has addressed the erratum with a firmware fix that modifies an internal configuration register (MCSR24). This fix ensures that the atomic instructions behave correctly without significant performance degradation, with single-core performance remaining unaffected and multi-core performance seeing only a slight drop. The fix is expected to be released in a firmware update before October 1, 2026. The investigation highlighted how modern hardware optimizations, such as vectorized memory copies in `glibc`, can interact with low-level atomic primitives in ways that are difficult to predict without rigorous, multi-architecture testing.