OpenAI unveiled its first AI accelerator chip, Jalapeño, on August 25, 2026. The chip delivers up to 13.4 petaflops of 4-bit compute while accessing 232 gigabytes of HBM4 memory at a bandwidth of 15.4 terabytes per second. Benchmarks cited by OpenAI show Jalapeño can reduce end-to-end latency by up to 3.6 times compared to Nvidia’s GB300 while consuming less power. The company completed the chip’s design from initial concept to first silicon in under 20 months, with only nine months separating the first register-transfer level code from tape-out—a timeline described by experts as “likely best in class today.” This rapid pace was achieved with a hardware team averaging fewer than 100 people over the project.
OpenAI’s acceleration relied on applying its large language models to the front‑end of chip design. The team used LLMs to enhance work with Accelerated Hardware Synthesis (XLS), an open‑source high‑level synthesis toolchain originally developed at Google. As Chris Leary, a member of OpenAI’s technical staff, explained, the AI was “much better at software‑looking things” because XLS allows designers to write chip logic in languages such as DSLX (Rust‑inspired) and C++, which XLS then converts to Verilog. This let engineers explore more design paths quickly while retaining human oversight, with Richard Ho, OpenAI’s vice president of hardware, noting that engineers remain the final arbiters but can “do things a lot faster.” In addition, once early silicon arrived from the foundry in May 2026, the team directed its internal LLMs at designing software to run benchmarks such as SemiAnalysis’s InferenceX. On DeepSeek’s multi‑head latent attention kernel benchmark, performance jumped from 0.31 percent of the theoretical ceiling (set by the chip’s compute and memory bandwidth) to 88.94 percent in roughly 40 hours—a result Ho said is repeatable and can shorten the interval between foundry delivery and production ramp‑up.
While LLMs proved effective for front‑end tasks and benchmark software, OpenAI found them less useful for backend design steps such as routing interconnects, completing clock and power specifications, and sending design information to the foundry—areas largely handled by manufacturing partner Broadcom. At IEEE Hot Chips 2026, Ho and Leary presented early results showing AI‑guided physical design optimization achieved a 10 percent area reduction for matrix multiplication units compared to an optimized human baseline, suggesting potential for broader AI integration in future generations. The company also confirmed access to internal LLMs fine‑tuned for chip design that are not publicly available, including precursors to GPT‑6 Astra. Ho and Leary indicated the workflow used for Jalapeño may look old‑fashioned compared to upcoming efforts, with plans to introduce more AI in verification, physical design, and automatic waveform analysis for debugging, though they stressed that chip design cannot be fully automated and that human engineers will remain essential.