Fujitsu is preparing the Monaka CPU, a next-generation processor that will succeed the A64FX chip first used in Japan's Fugaku supercomputer. The company says Monaka will launch in 2027, and it is already sampling the chip now.
The article opens by positioning Monaka as the successor to the A64FX chip that powered Japan's Fugaku supercomputer; this image shows the Fugaku system alongside the Monaka chip, directly linking the legacy system to its replacement.
Monaka is built around the Arm v9.3-A instruction set, which Fujitsu develops as a proprietary core design. It supports Arm's SVE2 vector extensions at 256 bits wide, with two 256-bit execution units and two 256-bit load/store units, plus support for FP8 and INT8 data types used in AI inference. Each core measures roughly 1.47 square millimeters, and the chip packs 144 of them.
The most unusual part of the design is its packaging. Instead of a single monolithic die, Monaka uses 3D chiplet integration: a 2nm compute die sits on top of a 5nm die that houses SRAM and I/O circuitry. The compute die is built on TSMC's N2P process, while the SRAM and I/O die uses TSMC's N5 technology. The two dies connect through face-to-face hybrid bonding, which shortens the signal path between the core and its last-level cache, and the I/O connects to the SRAM die via a silicon interposer.
Paragraph 3 describes Monaka's unusual 3D chiplet integration where a 2nm compute die sits atop a 5nm SRAM and I/O die connected by face-to-face hybrid bonding; this slide details the same cooling, latency, and power-delivery structure shown in the article.
Fujitsu says this disaggregated approach was chosen for power, performance, and cost. By separating the compute logic from the memory and I/O, the company can use the most suitable process for each component rather than forcing everything onto one node. The result is a 30 percent reduction in total silicon area for the 2nm die, which contributes to lower cost and a better performance balance. Placing the hotter core die on top also shortens the thermal path to cooling.
The platform supports two sockets per node, giving 288 cores total. On I/O, the chip carries 96 PCIe 6.0 lanes with CXL 3.0 support, and memory comes in the form of 12 channels of DDR5 rated above 8,000 megatransfers per second. The chip can be cooled by either liquid or air, and an LDO regulator enables per-core voltage and frequency scaling.
Fujitsu will ship Monaka in two variants. The high-performance SKU runs at 2.9 gigahertz base frequency with a 500-watt TDP, delivers 6,013 GFLOPs in double-precision floating point (DGEMM) and 96.2 tera-ops in INT8 at base clock, and uses liquid cooling. The high-efficiency SKU keeps the same 144 cores but runs at 2.1 gigahertz with a 350-watt TDP, delivering 4,355 GFLOPs and 69.7 tera-ops in INT8, with air cooling.
Paragraph 6 details the two Monaka variants — a 2.9 GHz, 500 W liquid-cooled high-performance SKU and a 2.1 GHz, 350 W air-cooled high-efficiency SKU — and this slide directly compares their core counts, TDP, cooling, frequencies, and estimated performance.
Fujitsu frames three goals for the chip: roughly double AI performance through architecture and an open ecosystem, more than 50 percent total cost of ownership reduction through ultra-low-voltage operation, and secure in-use data protection through confidential computing. The chip also supports flexible NUMA node configurations so that memory access can be tuned to software characteristics.
Looking further ahead, the company plans a Monaka-X chip for 2029 that will include SME2 vector extensions for AI and has been selected for the FugakuNext supercomputer. Monaka-X is also slated to integrate NVIDIA's NVLink Fusion for AI and high-performance computing.
Paragraph 8 looks ahead to the Monaka-X chip planned for 2029 and selected for the FugakuNext supercomputer; this roadmap slide visualizes the progression from the 7 nm A64FX through 2 nm Monaka to 1.4 nm Monaka-X for data centers, HPC, and AI.
One technical detail circulating about the chip is not supported by the source material. Figures such as 844 gigabytes per second of memory bandwidth and 4.3 to 6 teraflops of single-precision performance appear in external presentations referenced by readers, but the supplied article does not include them. Those numbers would need to come from the detailed presentations themselves, not from this coverage.
Monaka also carries a security feature set that includes ECC within the L1 and L2 caches, parity checks in execution units and registers, and a hardware instruction retry mechanism that can recover from transient errors. The chip is designed for both high-performance computing and AI workloads, with the company arguing that CPUs remain essential for throughput and precision in scientific computing while also handling orchestration and peripheral processing for agentic AI workloads.